1. Field of the Invention
The present invention relates to a solid-state image sensor, and more particularly to a solid-state image sensor using a charge sweep device for vertical charge transfer.
2. Description of the Prior Art
FIG. 1 is a block diagram of a conventional solid-state image sensor of a CSD (Charge Sweep Device) system shown in, for example, an article by M. Kimata et al., entitled "A 480.times.400 Element Image Sensor with a Charge Sweep Device," ISSCC, Digest of Technical Papers, 1985, pp. 100-101, an article by M. Yamawaki et al., entitled "A1/2" FORMAT COLOR IMAGE SENSOR WITH 485.times.510 PIXELS," Technical Digest of Electronic Imaging 85, 1985, pp. 91-94, and a technical report of the Television Society No. TEBS 101-6, ED 841 (Kimata et al.).
In FIG. 1, a conventional solid-state image sensor comprises photodetectors 111-148, CSDs 210-240 for vertical charge transfer, an interface section 300, a horizontal CCD 400, an output pre-amplifier 500, a transfer gate scanner 600, a CSD scanner 700, and interconnections 801-808.
The photodetectors 111-148 store signal charges corresponding to light signals irradiated. The charge sweep devices 210-240 transfer the signal charges from the photodetectors 111-148 in a vertical direction, respectively, the respective gates of the charge sweep devices including transfer gates as described below.
One pixel comprises a photodetector and a gate of the charge sweep device. The interface section 300 temporarily stores charges transferred by the charge sweep devices 210-240, and controls the transfer of the signal charges to the horizontal CCD 400. The transfer gate scanner 600 generates selection signals for indicating the selection of a transfer gate from a plurality of transfer gates included in a vertical line. The CSD scanner 700 supplies CSD driving signals to the charge sweep devices 210-240. Each gate of the charge sweep devices 210-240 is connected to each other by the interconnections 801-808. Both signals from the transfer gate scanner 600 and signals from the CSD scanner 700 are supplied to the respective gates of the charge sweep devices 210-240 by the interconnections 801-808.
FIG. 2 is a diagram showing in detail the construction of a pixel 100 as depicted in FIG. 1. In FIG. 2, a photodetector 125 includes a PN junction formed of a portion of a semiconductor substrate area and an area having a conductivity type different from that of the semiconductor substrate and a high impurity concentration. A gate 225 is one of the gates of a charge sweep device 220, a partial area 1 thereof being a transfer gate of a surface channel. An aluminum interconnection 805 is connected through a contact hole 3 to the gate 225. The area 2 is the charge sweep device of a buried channel.
FIG. 3 is a diagram showing a gate structure of a cross section of a solid-state image sensor taken along lines B--B'shown in FIG. 1 and also showing channel potentials.
Now, referring to FIGS. 1 to 3, the operation of a conventional solid-state image sensor is described. In FIG. 3, gates 221-228 are respective gates of a charge sweep device 220. An storage gate 321 and a storage control gate 322 comprise an interface section 300.
First, it is assumed that the respective potentials of the respective gates 221-228 of the charge sweep device 220 are "H","H","L","L","H","H","L" and "L" levels (H is high, and L is low). Then, the output of a CSD scanner 700 is rendered the high impedance state. In such a condition, a transfer gate, for example a gate 222, is rendered a "HH" level (higher than a "H" level) in a vertical line by driving a transfer gate scanner 600. At this "HH" level, it is possible to read out singal charges.
In FIG. 3, since a selection signal is applied to the gate 222, the signal charges of a photodetector 122 are read out (FIG. 3(a)). A CSD is divided into many small potential wells, and the signal charges read out from the photodetector are stored in a plurality of potential wells. For example, a signal charge is divided into Qs1, and Qs2, and transferred.
Then, the transfer gate scanner 600 is rendered the high impedance state, and subsequently, driving of a CSD is initiated. This driving is identical to that in an ordinal four-phase driving CCD. That is, the potentials at the gates 221-228 are "H", "H", "L", "L", "H", "H", "L" and "L" levels in the state shown in FIG. 3(b), which sequentially charge into "L", "H", "H", "L", "L", "H", "H" and "L" levels, "L", "L", "H", "H", "L", "L", "H" and "H" levels, "H", "L", "L", "H", "H", "L", "L" and "H" levels, and "H", "H", "L", "L", "H", "H", "L" and "L" levels corresponding to the state shown in FIG. 3(c).
By repeating this cycle, the signal charges are transferred to the storage gate 321, as shown in FIGS. 3(c)-3(e).
Finally, the potential of the storage control gate 322 becomes a "H" level, and the potential of the storage gate becomes a "L" level within a horizontal blanking interval, causing the signal charges to be transferred from the storage gate 321 to a horizontal CCD 400 as shown in FIG. 3(f). By repeating the above operation, the signal charges of all pixels are read out.
If transfer efficiency of the CSDs is insufficient, a charge Qr is left in a potential well, as shown in FIG. 3(d) Such left charge Qr can be added to a main signal within the storage gate by driving CSDs more times than the number of clock cycles necessary for sweeping the singal charges.
In a conventional solid-state image sensor, particularly including photodetectors formed by PN junction, the resistance value of transfer gates is increased as signal charges are read out, causing the transfer of the signal charges from a photodetector 125 to the charge sweep device area 2 to be imperfect. Since the solid-state image sensor using conventional CSDs have read out the charges from the photodetector 125 to the charge sweep device area 2 only one time within a horizontal scanning interval, they have encountered a difficulty in which lags would be created if the transfer of the signal charges became imperfect as described above.